Short company description

DABSTER GROUP IS A 25 M $ TALENT MANAGEMENT WORKFORCE SOLUTION PROVIDER IN IT AND ENGINEERING.

Requirements

Position Split of 32 -



General verification (Interrupts, Memory Map, RAS, boot) (Arm arch knowledge)  10

Core Sight Debug 1

System Scenarios/stress (Arm architecture knowledge) 2

Ethernet 4

Multi-die 1

Dynamic CDC  1

GLS  4

DFx 2

DFT  2

JTAG, BSCAN, LCS, provisioning 2

Production Die level functional testing 3

Responsibilities

General verification (Interrupts, Memory Map, RAS, boot) (Arm arch knowledge) -

The candidate is required to know ARM processor-based SOC architecture

The candidate is required to know ARM processors 



Core Sight Debug

The candidate is required to  have work experience on verification of Core Sight debug implement in a SOC



System Scenarios/stress (Arm architecture knowledge)-

The candidate is required to have a good understanding of ARM processor-based SOC architecture

Candidate is required to  have work experience in developing system level/ chip level tests for stress/performance testing 



Ethernet - The candidate is required to  have work experience in the verification of Ethernet subsystems 



Multi-die -

Candidate is required to have work experience in verification of die-to-die interconnect protocols such as AMBA CHI C2C or any other protocols

Or

Candidate should have a strong background in system-level testing.



Dynamic CDC - The candidate is required to have a good understanding of CDC issues and how to model the CDC issues in a simulation environment. 

GLS - The candidate is required to have good experience in gate-level simulations of complex designs.  

DFx - The candidate is required to have good experience with DFx features in a SOC / ASIC.   

DFT - The candidate is required to have good experience in DFT verification 

JTAG, BSCAN, LCS, provisioning - Candidate is required to have good experience in JTAG, Boundary scan, life cycle security feature verification 

Production Die level functional testing - The candidate is required to have experience with the development of silicon functional validation tests in a pre-silicon environment, such as development using emulators / FPGA prototypes etc